Patents
1 7,466,604 SRAM voltage control for improved operational margins
2 7,402,857 Flip FERAM cell and method to form same
3 7,390,721 Methods of base formation in a BiCMOS process
4 7,313,032 SRAM voltage control for improved operational margins
5 7,217,969 Flip FERAM cell and method to form same
6 7,193,262 Low-cost deep trench decoupling capacitor device and process of manufacture
7 7,190,007 Isolated fully depleted silicon-on-insulator regions by selective etch
8 7,186,573 Flip FERAM cell and method to form same
9 7,166,904 Structure and method for local resistor element in integrated circuit technology
10 7,087,486 Method for scalable, low-cost polysilicon capacitor in a planar DRAM
11 7,087,477 FinFET SRAM cell using low mobility plane for cell stability and method for forming
12 7,075,153 Grounded body SOI SRAM cell
13 7,057,180 Detector for alpha particle or cosmic ray
14 7,005,334 Zero threshold voltage pFET and method of making same
15 6,967,351 Finfet SRAM cell using low mobility plane for cell stability and method for forming
16 6,965,133 Method of base formation in a BiCMOS process
17 6,962,838 High mobility transistors in SOI and method for forming
18 6,946,376 Symmetric device with contacts self aligned to gate
19 6,917,221 Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits
20 6,900,505 Method of forming refractory metal contact in an opening, and resulting structure
21 6,891,419 Methods and apparatus for employing feedback body control in cross-coupled inverters
22 6,881,672 Selective silicide blocking
23 6,825,530 Zero Threshold Voltage pFET and method of making same
24 6,815,751 Structure for scalable, low-cost polysilicon DRAM in a planar capacitor
25 6,778,449 Method and design for measuring SRAM array leakage macro (ALM)
26 6,774,017 Method and structures for dual depth oxygen layers in silicon-on-insulator processes
27 6,762,121 Method of forming refractory metal contact in an opening, and resulting structure
28 6,700,163 Selective silicide blocking
29 6,646,305 Grounded body SOI SRAM cell
30 6,624,478 High mobility transistors in SOI and method for forming
31 6,624,475 SOI low capacitance body contact
32 6,614,124 Simple 4T static ram cell for low power CMOS applications
33 6,555,859 Flip FERAM cell and method to form same
34 6,515,317 Sidewall charge-coupled device with multiple trenches in multiple wells
35 6,512,296 Semiconductor structure having heterogenous silicide regions having titanium and molybdenum
36 6,498,096 Borderless contact to diffusion with respect to gate conductor and methods for fabricating
37 6,489,223 Angled implant process
38 6,476,445 Method and structures for dual depth oxygen layers in silicon-on-insulator processes
39 6,445,050 Symmetric device with contacts self aligned to gate
40 6,441,410 MOSFET with lateral resistor ballasting
41 6,420,746 Three device DRAM cell with integrated capacitor and local interconnect
42 6,395,624 Method for forming implants in semiconductor fabrication
43 6,387,596 Method of forming resist images by periodic pattern removal
44 6,380,063 Raised wall isolation device with spacer isolated contacts and the method of so forming
45 6,368,903 SOI low capacitance body contact
46 6,338,921 Mask with linewidth compensation and method of making same
47 6,335,272 Buried butted contact and method for fabricating
48 6,333,202 Flip FERAM cell and method to form same
49 6,300,228 Multiple precipitation doping process
50 6,294,419 Structure and method for improved latch-up using dual depth STI with impurity implant
51 6,268,286 Method of fabricating MOSFET with lateral resistor with ballasting
52 6,215,190 Borderless contact to diffusion with respect to gate conductor and methods for fabricating
53 6,187,679 Low temperature formation of low resistivity titanium silicide
54 6,187,617 Semiconductor structure having heterogeneous silicide regions and method for forming same
55 6,153,934 Buried butted contact and method for fabricating
56 6,144,086 Structure for improved latch-up using dual depth STI with impurity implant
57 6,140,171 FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication
58 6,022,766 Semiconductor structure incorporating thin film transistors, and methods for its manufacture
59 6,008,112 Method for planarized self-aligned floating gate to isolation
60 5,899,713 Method of making NVRAM cell with planar control gate
61 5,828,131 Low temperature formation of low resistivity titanium silicide
62 5,757,050 Field effect transistor having contact layer of transistor gate electrode material
63 5,744,384 Semiconductor structures which incorporate thin film transistors
64 5,677,563 Gate stack structure of a field effect transistor
65 5,675,185 Semiconductor structure incorporating thin film transistors with undoped cap oxide layers
66 5,672,901 Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
67 5,670,812 Field effect transistor having contact layer of transistor gate electrode material
68 5,510,295 Method for lowering the phase transformation temperature of a metal silicide
69 5,496,771 Method of making overpass mask/insulator for local interconnects
70 5,485,095 Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure
71 5,453,400 Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
2 7,402,857 Flip FERAM cell and method to form same
3 7,390,721 Methods of base formation in a BiCMOS process
4 7,313,032 SRAM voltage control for improved operational margins
5 7,217,969 Flip FERAM cell and method to form same
6 7,193,262 Low-cost deep trench decoupling capacitor device and process of manufacture
7 7,190,007 Isolated fully depleted silicon-on-insulator regions by selective etch
8 7,186,573 Flip FERAM cell and method to form same
9 7,166,904 Structure and method for local resistor element in integrated circuit technology
10 7,087,486 Method for scalable, low-cost polysilicon capacitor in a planar DRAM
11 7,087,477 FinFET SRAM cell using low mobility plane for cell stability and method for forming
12 7,075,153 Grounded body SOI SRAM cell
13 7,057,180 Detector for alpha particle or cosmic ray
14 7,005,334 Zero threshold voltage pFET and method of making same
15 6,967,351 Finfet SRAM cell using low mobility plane for cell stability and method for forming
16 6,965,133 Method of base formation in a BiCMOS process
17 6,962,838 High mobility transistors in SOI and method for forming
18 6,946,376 Symmetric device with contacts self aligned to gate
19 6,917,221 Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits
20 6,900,505 Method of forming refractory metal contact in an opening, and resulting structure
21 6,891,419 Methods and apparatus for employing feedback body control in cross-coupled inverters
22 6,881,672 Selective silicide blocking
23 6,825,530 Zero Threshold Voltage pFET and method of making same
24 6,815,751 Structure for scalable, low-cost polysilicon DRAM in a planar capacitor
25 6,778,449 Method and design for measuring SRAM array leakage macro (ALM)
26 6,774,017 Method and structures for dual depth oxygen layers in silicon-on-insulator processes
27 6,762,121 Method of forming refractory metal contact in an opening, and resulting structure
28 6,700,163 Selective silicide blocking
29 6,646,305 Grounded body SOI SRAM cell
30 6,624,478 High mobility transistors in SOI and method for forming
31 6,624,475 SOI low capacitance body contact
32 6,614,124 Simple 4T static ram cell for low power CMOS applications
33 6,555,859 Flip FERAM cell and method to form same
34 6,515,317 Sidewall charge-coupled device with multiple trenches in multiple wells
35 6,512,296 Semiconductor structure having heterogenous silicide regions having titanium and molybdenum
36 6,498,096 Borderless contact to diffusion with respect to gate conductor and methods for fabricating
37 6,489,223 Angled implant process
38 6,476,445 Method and structures for dual depth oxygen layers in silicon-on-insulator processes
39 6,445,050 Symmetric device with contacts self aligned to gate
40 6,441,410 MOSFET with lateral resistor ballasting
41 6,420,746 Three device DRAM cell with integrated capacitor and local interconnect
42 6,395,624 Method for forming implants in semiconductor fabrication
43 6,387,596 Method of forming resist images by periodic pattern removal
44 6,380,063 Raised wall isolation device with spacer isolated contacts and the method of so forming
45 6,368,903 SOI low capacitance body contact
46 6,338,921 Mask with linewidth compensation and method of making same
47 6,335,272 Buried butted contact and method for fabricating
48 6,333,202 Flip FERAM cell and method to form same
49 6,300,228 Multiple precipitation doping process
50 6,294,419 Structure and method for improved latch-up using dual depth STI with impurity implant
51 6,268,286 Method of fabricating MOSFET with lateral resistor with ballasting
52 6,215,190 Borderless contact to diffusion with respect to gate conductor and methods for fabricating
53 6,187,679 Low temperature formation of low resistivity titanium silicide
54 6,187,617 Semiconductor structure having heterogeneous silicide regions and method for forming same
55 6,153,934 Buried butted contact and method for fabricating
56 6,144,086 Structure for improved latch-up using dual depth STI with impurity implant
57 6,140,171 FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication
58 6,022,766 Semiconductor structure incorporating thin film transistors, and methods for its manufacture
59 6,008,112 Method for planarized self-aligned floating gate to isolation
60 5,899,713 Method of making NVRAM cell with planar control gate
61 5,828,131 Low temperature formation of low resistivity titanium silicide
62 5,757,050 Field effect transistor having contact layer of transistor gate electrode material
63 5,744,384 Semiconductor structures which incorporate thin film transistors
64 5,677,563 Gate stack structure of a field effect transistor
65 5,675,185 Semiconductor structure incorporating thin film transistors with undoped cap oxide layers
66 5,672,901 Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
67 5,670,812 Field effect transistor having contact layer of transistor gate electrode material
68 5,510,295 Method for lowering the phase transformation temperature of a metal silicide
69 5,496,771 Method of making overpass mask/insulator for local interconnects
70 5,485,095 Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure
71 5,453,400 Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits