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2011jun25_nonrandommm.pdf
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calhouniscas09subvt.pdf
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wang_cicc2010_paper.pdf
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steegen2005.pdf
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natzle2004.pdf
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wann2005.pdf
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lou2004.pdf
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hook2002a.pdf
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hook2002.pdf
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smeys2000.pdf
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cabral1997.pdf
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mann1993.pdf
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hook1995.pdf
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kosonocky2001.pdf
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miles1996.pdf
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clevenger1994.pdf
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c49_c54_jecs.pdf
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nowak1988.pdf
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modelfortisi2growth.pdf
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mann1995_c49_c54.pdf
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wellproximityeffect.pdf
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sse_mann2010assist.pdf
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Technical Papers

  • R. W. Mann, W. Abadeer, M. Brietwisch, O. Bula, J. Brown, B. Colwill, P.Cottrell, W. Crocco, S. Furkay, M. Hauser, T. Hook, D. Hoyniak, J. Johnson, C. Lam, R. Mih, J. Rivard, A. Moriwaki, E. Phipps, C. Putnam, B. Rainey, J. Toomey, M. Younus, “Ultralow-power SRAM technology”, IBM J. Res. & Dev. Vol. 47, no. 5/6 Sep/Nov 2003, p. 553-566
  • R.W. Mann, L.A. Clevenger, P.D. Agnello, F.R. White,"Silicides and local interconnects for high-performance VLSI applications: a review", IBM Journal of Res. and Dev., Vol.39, No.4 July P403-17 (1995).
  • Koburger, C.W., III Clark, W.F. Adkisson, J.W. Adler, E. Bakeman, P.E. Bergendahl, A.S. Botula, A.B. Chang, W. Davari, B. Givens, J.H. Hansen, H.H. Holmes, S.J. Horak, D.V. Lam, C.H. Lasky, J.B. Luce, S.E. Mann, R.W. Miles, G.L. Nakos, J.S. Nowak, E.J. Shahidi, G. Taur, Y. White, F.R. Wordeman, M.R."A half micron CMOS logic generation ", IBM J. Res. Dev. (USA) Vol.39, No.1-2 Jan. March 1995, p.215-27.
  • A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye, K. Chin, "Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells" , Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International 5-7 Dec. 2005 Page(s):659 - 662
  • T. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, R. Mann, "Lateral Ion Implant Straggle and Mask Proximity Effect", IEEE Trans. Elec. Dev. Vol. 50, no. 9, Sept 2003 p. 1946-1951
  • S. V. Kosonocky, M, Immediato, P. Cottrell, T. Hook, R. Mann, J. Brown, "Enhanced Mult-Threshold (MTCMOS) Circuits Using Variable Well Bias", Low Power Electronics and Design, International Symposium on, 2001. 6-7 Aug. 2001 Page(s):165 - 169
  • T.B.Hook, R.W.Mann, E.J.Nowak, "Titanium Silicide/Silicon Non-ohmic Contact Resitance for NFETs, PFETs, Diffused Resistors and NPNs in a BiCMOS Technology", IEEE Trans. Electron Devices 42 no. 4, 697 (1995).
  • Steegen, A.; Mo, R.; Mann, R.; Sun, M.-C.; Eller, M.; Leake, G.; Vietzke, D.; Tilke, A.; Guarin, F.; Fischer, A.; Pompl, T.; Massey, G.; Vayshenker, A.; Tan, W.L.; Ebert, A.; Lin, W.; Gao, W.; Lian, J.; Kim, J.-P.; Wrschka, P.; Yang, J.-H.; Ajmera, A.; Knoefler, R.; Teh, Y.-W.; Jamin, F.; Park, J.E.; Hooper, K.; Griffin, C.; Nguyen, P.; Klee, V.; Ku, V.; Baiocco, C.; Johnson, G.; Tai, L.; Benedict, J.; Scheer, S.; Zhuang, H.; Ramanchandran, V.; Matusiewicz, G.; Lin, Y.-H.; Siew, Y.K.; Zhang, F.; Leong, L.S.; Liew, S.L.; park, K.C; Lee, K.-W.; Hong, D.H.; Choi, S.-M.; Kaltalioglu, E.; Kim, S.O.; Naujok, M.; Sherony, M.; Cowley, A.; Thomas, A.; Sudijohno, J.; Schiml, T.; Ku, J.-H.; Yang, I.; "65nm cmos technology for low power applications" , Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International 5-7 Dec. 2005 Page(s):64 – 67
  • T. Hook, M. Brietwisch, J. Brown, P. Cottrell, D. Hoyniak, C. Lam, R. Mann, "Noise Margin and Leakage in Ultra-Low Leakage SRAM Cell Design", IEEE Trans. Elec. Dev. Vol. 49, no. 8, Aug. 2002, p. 1499-1501
  • Z. Luo, A. Steegen, M. Eller, R. Mann, C. Baiocco, P. Nguyen, L. Kim, M. Hoinkis, V. Ku, V. Klee, F. Jamin, P. Wrschka, P. Shafer, W. Lin, S. Fang, W. Tan, D. Park, R. Mo, J. Lian, D. Vietzke, C. Coppock, A. Vayshenker, T. Hook, V. Chan, K. Kim, A. Cowley, S. Kim, E. Kaltalioglu, B. Zhang, S. Marokkey, Y. Lin, M. Weybright, R. Rengarajan, J. Ku, T. Schiml, J. Sudijono, I. Yang, Clement Wann, "High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS Technology" , Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International 13-15 Dec. 2004 Page(s):661 - 664
  • R.W.Mann, "Interactions of Technology and Design in Nanoscale SRAM", Ph.D. Dissertation, Dec. 2010.
  • R.W.Mann and B.H.Calhoun, "New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm", In Proc. 12th International symposium on quality electronic design, ISQED 2011.
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